Efficient Implementation of KECCAK (SHA-3) Algorithm on FPGA

Cryptographic hash functions are used for digital signatures; message authentication codes (MACs) and other forms of authentication. National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. Hardware performance evaluation of the candidates is a vital part of this contest. This work is about an efficient FPGA implementation of Keccak that is one of the final round candidates of SHA-3. Our efficient implementation of KECCAK consists of two modules, one module is logic module and the other is memory module. In logic module actual KECCAK operations are performed while the memory module is used to store intermediate values during the calculation of Keccak Permutation: Logic module is sub divide into control module and data path module. Control module generates control signals for data path module and address signal for memory module. The proposed memory module can also be used as shared memory with other algorithms. We show our results in the form of chip area consumption and compare these results with other reported implementations of Keccak.