Cache write generate for parallel image processing on shared memory architectures

被引：1

作者：

Wittenbrink, CM ^{[1
]}

Somani, AK ^{[1
]}

Chen, CH ^{[1
]}

机构：

[1] UNIV WASHINGTON, DEPT ELECT ENGN, SEATTLE, WA 98195 USA

来源：

IEEE TRANSACTIONS ON IMAGE PROCESSING | 1996年 / 5卷 / 07期

关键词：

D O I：

10.1109/83.502410

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.

引用

页码：1204 / 1208

页数：5

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