A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

被引:2
|
作者
Choe, Young-Joe [1 ]
Nam, Hyohyun [1 ]
Park, Jung-Dong [1 ]
机构
[1] Dongguk Univ, Div Elect & Elect Engn, Seoul 04620, South Korea
关键词
CMOS; power amplifier; power supply rejection ratio; wireless; DESIGN;
D O I
10.3390/electronics8091043
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push-pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Omega load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm(2) without pads.
引用
收藏
页数:9
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