Physics of electronic transport in low-dimensionality materials for future FETs

被引：0

作者：

Fischetti, M. V. ^{[1
]}

Vandenberghe, W. G. ^{[1
]}

Fu, Bo ^{[1
]}

Narayanan, S. ^{[1
]}

Kim, J. ^{[1
]}

Ong, Z. -Y. ^{[1
]}

Suarez-Negreira, A. ^{[1
]}

Sachs, C. ^{[1
]}

Aboud, S. J. ^{[2
]}

机构：

[1] Univ Texas Dallas, Dept Mat Sci & Engn, Richardson, TX 75080 USA

[2] Stanford Univ, Energy Resources Engn, Stanford, CA 95306 USA

来源：

2014 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD) | 2014年

关键词：

EFFECT TRANSISTOR BISFET;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We show that scaling rules, quantum confinement in thin bodies, and the resulting gate leakage render imperative the use of low-dimensionality materials as channels in devices scaled beyond the 10 nm gate length. We then consider a few examples of two-dimensional materials of great interest, graphene and bilayer graphene, and show how the dielectric environment (gate and interlayer insulators, nearby gates) has a dramatically strong effect on the electronic properties of systems such as supported graphene, nanoribbons, and graphene bilayers in which a Bose-Einstein exciton condensation has been predicted to occur at high temperature. Finally, we consider the novel concept of devices based on monolayer tin ('stannanane') as a topological insulator.

引用

页码：1 / 4

页数：4

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