Mixed-mode simulations for power-on ESD analysis

被引：0
|
作者：
Scholz, M. [1 ]
Shibkov, A.
Chen, S. -H.
Linten, D.
Thijs, S.
Sawada, M.
Vandersteen, G. [1 ]
Groeseneken, G.
机构：
[1] IMEC, B-3001 Louvain, Belgium
来源：
2012 34TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD) | 2012年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The transient behavior of an on-chip ESD protection device and off-chip components under system-level ESD stress is analyzed with mixed-mode simulations. A detailed transient analysis is required to prevent thermal failure when no supply voltage is applied and to prevent latchup when the supply voltage is applied.
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页数：9
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