An upper bound for 3D slicing floorplans

被引：5

作者：

Salewski, S ^{[1
]}

Barke, E ^{[1
]}

机构：

[1] Univ Hannover, Inst Microelect Circuits & Syst, D-30167 Hannover, Germany

来源：

ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/ASPDAC.2002.994982

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As the impact of interconnect on IC performance and chiparea in deep submicron design increases, research activities on technologies for three-dimensional integrated circuits intensity Nevertheless, there is not much work, done on the automation of 3D-1ayout design. In this paper we survey slicing structures for 3D floorplans. We present an tipper bound for the volume of such floorplans, which shows the usability of slicing structures for three-dimensional floorplanning.

引用

页码：567 / 572

页数：4

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