A 13.1-to-28GHz Fractional-N PLL in 32nm SOI CMOS with a ΔΣ Noise-Cancellation Scheme

被引：0
|
作者：
Ferriss, Mark [1 ]
Sadhu, Bodhisatwa [1 ]
Rylyakov, Alexander [1 ]
Ainspan, Herschel [1 ]
Friedman, Daniel [1 ]
机构：
[1] IBM Res, Yorktown Hts, NY 10598 USA
来源：
2015 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC) | 2015年 / 58卷
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：192 / U267
页数：3
相关论文
共 50 条
  • [41] A 28nm CMOS Digital Fractional-N PLL with-245.5dB FOM and a Frequency Tripler For 802.11abgn/ac Radio
    Gao, Xiang
    Tee, Luns
    Wu, Wanghua
    Lee, Kun-Seok
    Paramanandam, Arvind Anumula
    Jha, Anuranjan
    Liu, Norman
    Chan, Edwin
    Lin, Li
    2015 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2015, 58 : 166 - U229
  • [42] A Fractional-N Digital PLL with Background-Dither-Noise-Cancellation Loop Achieving <-62.5dBc Worst-Case Near-Carrier Fractional Spurs in 65nm CMOS
    Ho, Cheng-Ru
    Chen, Mike Shuo-Wei
    2018 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC), 2018, : 394 - +
  • [43] A Compact 0.8-6GHz Fractional-N PLL with Binary-Weighted D/A Differentiator and Offset-Frequency & Modulator for Noise and Spurs Cancellation
    Jian, Heng-Yu
    Xu, Zhiwei
    Wu, Yi-Cheng
    Chang, Frank
    2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : 186 - +
  • [44] A 7.7∼10.3GHz 5.2mW-247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS
    Liao, Dongyi
    Dai, Fa Foster
    2020 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2020,
  • [45] A 2.4-GHz Reference Doubled Fractional-N PLL with Dual Phase Detector in 0.13-μm CMOS
    Lee, Woojae
    Cho, SeongHwan
    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 1328 - 1331
  • [46] Low-Noise Fractional-N PLL Design with Mixed-Mode Triple-Input LC VCO in 65nm CMOS
    Sun, Yuanfeng
    Yu, Xueyi
    Rhee, Woogeun
    Ko, Sangsoo
    Choo, Wooseung
    Park, Byeong-Ha
    Wang, Zhihua
    2010 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS RFIC SYMPOSIUM, 2010, : 61 - 64
  • [47] An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL
    Lee, Jong Mi
    Jee, Dong-Woo
    Kim, Byungsub
    Park, Hong-June
    Sim, Jae-Yoon
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15 (03) : 342 - 348
  • [48] A 60GHz, Linear, Direct Down-Conversion Mixer with mm-Wave Tunability in 32nm CMOS SOI
    Sanduleanu, M. A. T.
    Valdes-Garcia, A.
    Liu, Y.
    Parker, B.
    Shlafman, Shlomo
    Sheinman, Benny
    Elad, Danny
    Reynolds, Scott
    Friedman, Daniel
    2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2013,
  • [49] A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC
    Xu, Zule
    Miyahara, Masaya
    Okada, Kenichi
    Matsuzawa, Akira
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (10) : 2345 - 2356
  • [50] A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS
    Liu, Hanli
    Siriburanon, Teerachot
    Nakata, Kengo
    Deng, Wei
    Son, Ju Ho
    Lee, Dae Young
    Okada, Kenichi
    Matsuzawa, Akira
    IEICE TRANSACTIONS ON ELECTRONICS, 2018, E101C (04): : 187 - 196
12345