Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

被引:50
|
作者
Rao, Padmakumar R. [1 ]
Wang, Xinyang [1 ]
Theuwissen, Albert J. P. [1 ,2 ]
机构
[1] Delft Univ Technol, Elect Instrumentat Lab, Delft, Netherlands
[2] Harvest Imaging, Bree, Belgium
关键词
CMOS image sensors; gated-diodes; radiation hardness; STI; spectral response;
D O I
10.1016/j.sse.2008.04.023
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive too]. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to gamma-ray irradiation is Studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to gamma-ray irradiation. Results further Suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments. (C) 2008 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1407 / 1413
页数:7
相关论文
共 50 条
  • [41] Novel octagonal device structure for output transistors in deep-submicron low-voltage CMOS technology
    Ker, MD
    Wu, TS
    IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, : 889 - 892
  • [42] Challenges to accuracy for the design of deep-submicron RF-CMOS circuits
    Yoshitomi, Sadayuki
    PROCEEDINGS OF THE ASP-DAC 2007, 2007, : 438 - 441
  • [43] Gate delay time evaluation structure for deep-submicron CMOS LSIs
    Nishimura, K
    Urano, M
    Ino, M
    Takeya, K
    Ishihara, T
    Kado, Y
    Inokawa, H
    ICMTS 1996 - 1996 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, PROCEEDINGS, 1996, : 135 - 138
  • [44] Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology
    Chang, HH
    Ker, MD
    Wu, JC
    SOLID-STATE ELECTRONICS, 1999, 43 (02) : 375 - 393
  • [45] An evaluation of deep-submicron CMOS design optimized for operation at 77 K
    Foty, Daniel
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2006, 49 (02) : 97 - 105
  • [46] Deep Image Demosaicing for Submicron Image Sensors
    Kim, Irina
    Song, Seongwook
    Chang, Soonkeun
    Lim, Sukhwan
    Guo, Kai
    JOURNAL OF IMAGING SCIENCE AND TECHNOLOGY, 2019, 63 (06)
  • [47] Estimation of the defective IDDQ caused by shorts in deep-submicron CMOS ICs
    Rodriguez-Montanes, R
    Figueras, J
    DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, : 490 - 494
  • [48] FABRICATION AND DELAY-TIME ANALYSIS OF DEEP-SUBMICRON CMOS DEVICES
    NARA, Y
    DEURA, M
    GOTO, K
    YAMAZAKI, T
    FUKANO, T
    SUGII, T
    IEICE TRANSACTIONS ON ELECTRONICS, 1995, E78C (03) : 293 - 298
  • [49] An evaluation of deep-submicron CMOS design optimized for operation at 77 K
    Daniel Foty
    Analog Integrated Circuits and Signal Processing, 2006, 49 : 97 - 105
  • [50] DEEP-SUBMICRON CMOS WARMS UP TO HIGH-SPEED LOGIC
    MASAKI, A
    IEEE CIRCUITS AND DEVICES MAGAZINE, 1992, 8 (06): : 18 - 24