Address RF Multi-site Test Efficiency Challenge

To economically test RF devices in high volume, one important approach is to make multi-site test. But some features of RF test challenges the multi-site efficiency. These challenges include the data uploading, data processing and the idle waiting behavior in semi-parallel test. In this paper, we will introduce the ATE architecture and solution which takes advantage of latest CPU, DSP and HSIO technology to handle above-mentioned challenges. Thus, the good architecture achieves high efficiency multi-site RF test, lower the cost of test.