Challenges and opportunities in advanced Ge pMOSFETs

被引:78
|
作者
Simoen, E. [1 ]
Mitard, J. [1 ]
Hellings, G. [1 ]
Eneman, G. [1 ]
De Jaeger, B. [1 ]
Witters, L. [1 ]
Vincent, B. [1 ]
Loo, R. [1 ]
Delabie, A. [1 ]
Sioncke, S. [1 ]
Caymax, M. [1 ]
Claeys, C. [1 ,2 ]
机构
[1] IMEC, B-3001 Louvain, Belgium
[2] EE Dept KU Leuven, B-3001 Louvain, Belgium
关键词
Germanium; CMOS; Surface passivation; High-k gate stack; Hole mobility; ATOMIC LAYER DEPOSITION; HIGH-K/GE PMOSFETS; HIGH-QUALITY GE; HIGH-MOBILITY; STRAINED-GE; HOLE-MOBILITY; SILICON-GERMANIUM; EPITAXIAL-GROWTH; SI WAFERS; P-MOSFETS;
D O I
10.1016/j.mssp.2012.04.017
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper aims at reviewing the state-of-the art of Ge pMOSFETs for future high-performance CMOS devices. Key in the development is the integration of a Ge channel on a silicon platform and the passivation of the interface between the high-k gate stack and the substrate. The different routes will be critically discussed in view of optimizing the on-current related to a high low-field hole mobility and reducing the off-current and the short-channel effects. Finally, an outlook on future technology developments will be formulated. (C) 2012 Elsevier Ltd. All rights reserved.
引用
收藏
页码:588 / 600
页数:13
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