A technique for fault tolerance assessment of COTS based systems

被引:0
|
作者
Alexandersson, R [1 ]
Chaitanya, DK [1 ]
Öhman, P [1 ]
Siraj, Y [1 ]
机构
[1] Chalmers Univ Technol, Dept Comp Engn, SE-41296 Gothenburg, Sweden
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This paper investigates the feasibility of emulating source code software faults directly in Java byte code. Experimental results show that software defects introduced in source code can be emulated in Java byte code with a high level of confidence. This makes it possible to validate the dependability of Java programs with respect to realistic software defects embedded within the COTS components used without the need to know the source code, It is first investigated with good results how well the fault locations found at the byte code level map to the source code. The behaviors of the byte code level mutants are then compared with the corresponding source code mutant behavior. In a back-to-back comparative study with mutants based on ten representative programming defects, no difference in the program behavior between source and byte code level mutants could be distinguished.
引用
收藏
页码:165 / 178
页数:14
相关论文
共 50 条
  • [41] Architecture Level Fault Tolerance Modeling for SOA Based Systems
    Goel, Swati
    Gupta, Ratneshwer
    SMART SYSTEMS: INNOVATIONS IN COMPUTING (SSIC 2021), 2022, 235 : 1 - 9
  • [42] Fault tolerance via endocrinologic based communication for multiprocessor systems
    Greensted, AJ
    Tyrrell, AM
    EVOLVABLE SYSTEMS: FROM BIOLOGY TO HARDWARE, PROCEEDINGS, 2003, 2606 : 24 - 34
  • [43] Fault Tolerance Logging-based Model for Deterministic Systems
    Pereira, Oscar Mortagua
    Simoes, David
    Aguiar, Rui L.
    DATA: PROCEEDINGS OF THE 5TH INTERNATIONAL CONFERENCE ON DATA MANAGEMENT TECHNOLOGIES AND APPLICATIONS, 2016, : 119 - 126
  • [44] Fault Tolerance Through Redundant Execution on COTS Multicores: Exploring Trade-offs
    Shen, Yanyan
    Heiser, Gernot
    Elphinstone, Kevin
    2019 49TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS (DSN 2019), 2019, : 188 - 200
  • [45] A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories
    Costenaro, Enrico
    Violante, Massimo
    Alexandrescu, Dan
    2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2011,
  • [46] The implementation of a COTS based fault tolerant avionics bus architecture
    Chau, S
    Luong, H
    Charlan, W
    Fukuhara, R
    Holmberg, E
    Jones, P
    Pixler, G
    2000 IEEE AEROSPACE CONFERENCE PROCEEDINGS, VOL 7, 2000, : 297 - 305
  • [47] A robust fault protection strategy for a COTS-Based spacecraft
    Jackson, Bill
    2007 IEEE AEROSPACE CONFERENCE, VOLS 1-9, 2007, : 2571 - 2581
  • [48] Time-lag duplexing - A fault tolerance technique for online transaction processing systems
    Chandra, A
    Bossen, DC
    PACIFIC RIM INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT SYSTEMS, PROCEEDINGS, 1997, : 202 - 207
  • [49] Virtual Machine Migration as a Fault Tolerance Technique for Embedded Real-Time Systems
    Groesbrink, Stefan
    2014 IEEE EIGHTH INTERNATIONAL CONFERENCE ON SOFTWARE SECURITY AND RELIABILITY - COMPANION (SERE-C 2014), 2014, : 7 - 12
  • [50] Double Modular Redundancy (DMR) Based Fault Tolerance Technique for Combinational Circuits
    Sheikh, Ahmad T.
    El-Maleh, Aiman H.
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2018, 27 (06)