A 10 GHz Low-Power Multi-Modulus Frequency Divider using Extended True Single-Phase Clock (E-TSPC) Logic

被引：0

作者：

Jung, M. ^{[1
]}

Fuhrmann, J. ^{[1
]}

Ferizi, A. ^{[1
]}

Fischer, G. ^{[1
]}

Weigel, R. ^{[1
]}

Ussmueller, T. ^{[1
]}

机构：

[1] Univ Erlangen Nurnberg, Inst Elect Engn, D-91058 Erlangen, Germany

来源：

2012 7TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC) | 2012年

关键词：

DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a multi-modulus frequency divider (MMD) based on the Extended True Single-Phase Clock (E-TSPC) Logic. The MMD consists of four cascaded divide-by-2/3 E-TSPC cells. The basic functionality of the MMD and the E-TSPC 2/3 divider are explained. The whole design was implemented in an [0.13] m CMOS process from IBM. Simulation and measurement results of the MMD are shown. Measurement results indicates a maximum operating frequency of [10] GHz and a power consumption of [4] mW for each stage. These results are compared to other state of the art dual modulus E-TSPC dividers, showing the good position of this design relating to operating frequency and power consumption.

引用

页码：508 / 511

页数：4

共 27 条

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