Network Monitoring Adaptor for 10Gbps Technology using FPGA

被引:0
|
作者
Martinek, Tomas [1 ]
Korenek, Jan [1 ]
Novotny, Jiri [2 ]
机构
[1] Brno Univ Technol, Fac Informat Technol, Bozetechova 2, Brno 61266, Czech Republic
[2] Masaryk Univ, Fac Informat, Brno 60200, Czech Republic
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes the architecture of a passive network monitoring adaptor dedicated to 10 Gbps technology. The proposed adaptor is able to produce statistics of input data flows, provide deterministic and stochastic packet sampling and search for specified patterns in packets bodies-payload checking. The architecture is designed for an FPGA platform and composed of several cooperating application specific processors and control units. This paper presents and evaluates the first implementation on existing hardware.
引用
收藏
页码:143 / 150
页数:8
相关论文
共 50 条
  • [1] WHEN IS 10GBPS NOT 10GBPS?
    Barry, Dan Joe
    [J]. ELECTRONICS WORLD, 2009, 115 (1883): : 18 - 20
  • [2] Achieving 10Gbps Network Processing: Are We There Yet?
    Govindarajan, Priya
    Makineni, Srihari
    Newell, Donald
    Iyer, Ravi
    Huggahalli, Ram
    Kumar, Amit
    [J]. HIGH PERFORMANCE COMPUTING - HIPC 2008, PROCEEDINGS, 2008, 5374 : 518 - 528
  • [3] 10Gbps LDPC编码器的FPGA设计
    袁瑞佳
    白宝明
    童胜
    [J]. 电子与信息学报, 2011, 33 (12) : 2942 - 2947
  • [4] Design and implementation of a network processor based 10Gbps network traffic generator
    Shah, Sanket
    Bansod, Tularam M.
    Singh, Amit
    [J]. DISTRIBUTED COMPUTING AND NETWORKING, PROCEEDINGS, 2006, 4308 : 269 - 275
  • [5] 10Gbps Bidirectional Transmission GPON Network Based on Single Fiber
    Islam, Taifoor Ul
    Hussain, Aftab
    Ashraf, Syed Shees
    [J]. 2015 INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES (ICET), 2015,
  • [6] Fast, large-scale string match for a 10Gbps FPGA-based network Intrusion Detection System
    Sourdis, I
    Pnevmatikatos, D
    [J]. FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2003, 2778 : 880 - 889
  • [7] Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA
    Yang, Dan
    Xu, Xuhan
    Chen, Tianyang
    Chen, Yanhao
    Zhang, Junjie
    [J]. SENSORS, 2023, 23 (10)
  • [8] 10Gbps 2-fiber ring network transmission system
    Tanabe, T
    Arai, S
    Asakura, N
    Chuzenji, T
    Fukushima, M
    [J]. NEC RESEARCH & DEVELOPMENT, 1999, 40 (03): : 361 - 365
  • [9] An FPGA-Based Change-Point Detection for 10Gbps Packet Stream
    Iwata, Takuma
    Nakamura, Kohei
    Tokusashi, Yuta
    Matsutani, Hiroki
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2019, E102D (12) : 2366 - 2376
  • [10] A 12.5Gbps half-rate CMOS CDR circuit for 10Gbps network applications
    Takasoh, J
    Yoshimura, T
    Kondoh, H
    Higashisaka, N
    [J]. 2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, : 268 - 271