Performance evaluation of a multiple-threaded multiple-pipelined Java']Java processor

Executing Java bytecodes natively by high-performance Java processors has been becoming more attractive as network computing gains importance. This paper proposes a multiple-threaded multiple-pipelined Java processor architecture and presents the design and implementation of a tracer which gathers desirable information on the behavior of Java programs and an architectural simulator which investigates Java bytecode instruction/thread level parallelism and predicts the performance of the proposed processor. We use multiple pipelined functional units (FUs) to execute multiple bytecodes in parallel in our processor model. The types of FUs and the number of each type of FUs needed for executing Java bytecodes are also investigated. Our simulation results show that a Java processor with two issuing slots could achieve an average 5.86 IPC (instructions per cycle) performance. The simulator also predicts the utilization of FUs with different processor configurations. Since the processor configurations can be changed easily just by changing a configuration file, this simulator and the simulation results can be helpful for turning the processor design decisions.