Effect of Interface States (Dit) at the a-Si/c-Si Interface on the Performance of Thin Film a-Si/c-Si/c-Si Heterojunction Solar Cells

The effect of interface states (D-it) at the a-Si/c-Si interface on the performance of a-Si(n(+))/c-Si(p)/c-Si(p(+)) heterojunction solar cells is investigated using Physics Based TCAD simulation. D-it is simulated as Gaussian distribution with peak ranging from 1x10(9) cm(-2) to 1x10(15) cm(-2). In addition, c-Si layers of 4, 3, 2, 1, and 0.5 mu m are simulated to study the effect of thickness, while the lifetime of the c-Si layer is varied from 1ns to 1ms. For a 2 mu m c-Si layer with 100 mu s lifetime, the results show a drop in open-circuit voltage (V-oc) from 0.68 V to 0.52 V as D-it increases from 1x10(9) cm(-2) to 1x10(15) cm(-2). The efficiency drops from 8% to 6%. The short-circuit current (J(sc)) does not change with D-it and is only a function of thickness and lifetime