An Analog Phase Prediction Based Fractional-N PLL

A synthesizer design for achieving high frequency resolution and stability is described. Fractional-N resolution is achieved, without using the classical dual-modulus divider, by exploiting the predictable phase evolution. The predicted phase is added in the feed-forward path within an integer-N analog PLL. A digital pulse generator (DPG) cancels the expected phase difference between the reference and feedback signal. A high-speed current-steering DAC increases the effective pulse width resolution overcoming the limit imposed by the VCO frequency. A novel ping-pong swallow counter topology masks the pipeline delay of a synchronous frequency divider used in the DPG. The architecture has been designed and simulated in a CMOS 0.13 mu m technology. For a 5 GHz VCO and 100 MHz reference, the synthesizer exhibits 1.5 Hz frequency steps with the wideband performance of a conventional charge pump PLL.