Radiation Hardened Pulsed-Latches in 65-nm CMOS

被引：0

作者：

Shah, Jaspal Singh ^{[1
]}

Sachdev, Manoj ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, 200 Univ Ave West, Waterloo, ON N2L 3G1, Canada

来源：

2016 IEEE CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (CCECE) | 2016年

关键词：

Flip-flop; soft error; neutron; latch; CMOS; hardened by design (HBD); SRAM; pulsed-latch; Single Event Upset (SEU); soft-error rate (SER); FLIP-FLOPS; PERFORMANCE;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents soft error robust pulsed latches based on popular hardened cells. Additional circuit techniques are incorporated to improve double node upset. Simulation results show a 4x improvement for double node upset in the critical charge for the presented latches compared to the reported hardened latches.

引用

页数：4

共 50 条

[41] A 130-GHz OOK Transmitter in 65-nm CMOS Technology
Kim, Namhyung
Son, Heekang
Kim, Dong-Hyun
Rieh, Jae-Sung
2016 IEEE 16TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF), 2016, : 113 - 115
[42] An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology
Qingyu Chen
Haibin Wang
Li Chen
Lixiang Li
Xing Zhao
Rui Liu
Mo Chen
Xuantian Li
Journal of Electronic Testing, 2016, 32 : 385 - 391
[43] A 65-nm CMOS Fluorescence Sensor for Dynamic Monitoring of Living Cells
Aghlmand, Fatemeh
Hu, Chelsea Y.
Sharma, Saransh
Pochana, Krishna
Murray, Richard M.
Emami, Azita
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2023, 58 (11) : 3003 - 3019
[44] V-band balanced resistive mixer in 65-nm CMOS
Varonen, Mikko
Karkkainen, Mikko
Halonen, Kari A. I.
ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2007, : 360 - 363
[45] A 300-GHz Fundamental Oscillator in 65-nm CMOS Technology
Razavi, Behzad
2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2010, : 113 - 114
[46] A 65-nm CMOS Constant Current Source With Reduced PVT Variation
Wang, Dong
Tan, Xiao Liang
Chan, Pak Kwong
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (04) : 1373 - 1385
[47] A 204-234.5-GHz Wideband Amplifier in 65-nm CMOS
Qi, Hao
Wen, Jincai
An, Donggang
Wang, Xun
2019 PHOTONICS & ELECTROMAGNETICS RESEARCH SYMPOSIUM - FALL (PIERS - FALL), 2019, : 3000 - 3004
[48] A 60-GHz SPST Switch in 65-nm CMOS Technology
Apriyana, Anak Agung Alit
Zhang, Yue Ping
2014 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT): SILICON TECHNOLOGY HEATS UP FOR THZ, 2014,
[49] A Stereo Earphone Driver with Volume Control in 65-nm CMOS Technology
Tanzil, Alexander
Dasgupta, Uday
2009 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY: SYNERGY OF RF AND IC TECHNOLOGIES, PROCEEDINGS, 2009, : 351 - 354
[50] 65-nm CMOS, W-band receivers for imaging applications
Tang, K. W.
Khanpour, M.
Garcia, P.
Garnier, C.
Voinigescu, S. P.
PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, : 749 - +

← 1 2 3 4 5 →