Radiation Hardened Pulsed-Latches in 65-nm CMOS

被引：0
|
作者：
Shah, Jaspal Singh [1 ]
Sachdev, Manoj [1 ]
机构：
[1] Univ Waterloo, Dept Elect & Comp Engn, 200 Univ Ave West, Waterloo, ON N2L 3G1, Canada
来源：
2016 IEEE CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (CCECE) | 2016年
关键词：
Flip-flop; soft error; neutron; latch; CMOS; hardened by design (HBD); SRAM; pulsed-latch; Single Event Upset (SEU); soft-error rate (SER); FLIP-FLOPS; PERFORMANCE;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
This paper presents soft error robust pulsed latches based on popular hardened cells. Additional circuit techniques are incorporated to improve double node upset. Simulation results show a 4x improvement for double node upset in the critical charge for the presented latches compared to the reported hardened latches.
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页数：4
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