An Electrode-Impedance-Aware Neurostimulator ASIC That Achieves Low-Power Consumption and Fast Charge Balancing

Implantable neural stimulation is becoming increasingly popular for treating neurologically impaired patients. The charge balancing of the stimulus pulses is of paramount importance for the long-term safety of the electrode-tissue interface. This paper presents a novel neurostimulator ASIC in which two novel charge balancing schemes are proposed. One is based on acquiring the access resistance part of the inter-electrode impedance. The other scheme is based on acquiring the double-layer capacitance part of the interelectrode impedance. This is in sharp contrast to the existing electrode impedance-aware charge balancing scheme which requires ADCs and computes the net charge in the digital domain. Hence the new impedance-aware charge-balancing scheme is more power friendly and can achieve charge balancing more quickly. The impedance-aware stimulator ASIC has been implemented using X-FAB's 180-nm CMOS process. The simulation results suggest that good charge balancing is achieved as the residual voltage on the electrode after the charge compensation reduces to 3.51 mV and 0.44 mV under the RS-based and Cdl-based charge balancing schemes, respectively.