On the FPGA-Based Hardware Implementation of Digital Glucose Regulators for Type 2 Diabetic Patients

In this paper, the hardware implementation of a quantized sampled-data glucose regulator for type 2 diabetic patients (T2DM) is investigated and proposed. The considered control strategy, designed through a model based approach, includes a glucose regulator that makes use of only glucose measurements. In order to validate the designed digital architecture implementing the controller embedded into the glucose regulator, a prototype has been developed on a Field Programmable Gate Array (FPGA) board (Artix 7 by Xilinx). The performances of the proposed digital system have been evaluated both in open loop (the controller only) and in closed loop (the complete glucose regulator) by employing a comprehensive mathematical model of a virtual patient recognized by the FDA for the pre-clinical validation of glucose control strategies. The achieved experimental results are in a good agreement with the numerical data coming from the theoretical model. In particular, by comparing the conducted simulations with the performed measurements a very high accuracy has been achieved with errors lower than 1 %. The implemented hardware solution of the digital controller is cable to process the input glucose data in about 1.1 mu s with a total power consumption of about 36 mW. These achievements open the way for further investigation on the digital architectures for glucose regulators to be integrated as VLSI System-on-Chips and/or Lab-on-Chips for portable, wearable and implantable solutions in real biomedical scenarios and applications.