Optimization of Subthreshold Swing and Hysteresis in Hf0.5Zr0.5O2-Based MoS2 Negative Capacitance Field-Effect Transistors by Modulating Capacitance Matching

被引:6
|
作者
Guo, Xiaowei [1 ]
Wang, Fang [1 ]
Ma, Zexia [1 ]
Shan, Xin [1 ]
Lin, Xin [1 ]
Ji, Yujing [1 ]
Zhao, Xuanyu [2 ]
Feng, Yulin [3 ]
Han, Yemei [1 ]
Xie, Yangyang [1 ]
Song, Zhitang [4 ]
Zhang, Kailiang [1 ]
机构
[1] Tianjin Univ Technol, Sch Integrated Circuit Sci & Engn, Tianjin Key Lab Film Elect & Commun Devices, Tianjin 300384, Peoples R China
[2] Fudan Univ, Sch Microelect, Shanghai 200433, Peoples R China
[3] Beijing Informat Sci & Technol Univ, Minist Educ Optoelect Measurement Technol & Instru, Key Lab, Beijing 100192, Peoples R China
[4] Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Funct Mat Informat, Shanghai 200050, Peoples R China
基金
中国国家自然科学基金;
关键词
MoS2; NCFET; subthreshold swing; hysteresis; Hf0 5Zr0 5O2 thin film; capacitance matching; FILMS;
D O I
10.1021/acsami.3c04595
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
Negative capacitance field effect transistors made ofHf(0.5)Zr(0.5)O(2) (HZO) are one of themost promisingcandidates for low-power-density devices because of the extremelysteep subthreshold swing and high open-state currents resulting fromthe addition of ferroelectric materials in the gate dielectric layer.In this paper, HZO thin films were prepared by magnetron sputteringcombined with rapid thermal annealing. Their ferroelectric propertieswere adjusted by changing the annealing temperature and the thicknessof HZO. Two-dimensional MoS2 back-gate negative capacitancefield-effect transistors (NCFETs) based on HZO were prepared as well.Different annealing temperatures, thicknesses of HZO thin films, andAl(2)O(3) thicknesses were studied to achieve optimalcapacitance matching, aiming to reduce both the subthreshold swingof the transistor and the hysteresis of the NCFET. The NCFET exhibitsa minimum subthreshold swing as low as 27.9 mV/decade, negligiblehysteresis (& SIM;20 mV), and the I (ON)/I (OFF) of up to 1.58 x 10(7). Moreover, a negative drain-induced barrier lowering effect anda negative differential resistance effect have been observed. Thissteep-slope transistor is compatible with standard CMOS manufacturingprocesses and attractive for 2D logic and sensor applications as wellas future energy-efficient nanoelectronic devices with scaled powersupplies.
引用
收藏
页码:31617 / 31626
页数:10
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