Ternary combinational logic gate design based on tri-valued memristors

被引:4
|
作者
Li, Xiao-Jing [1 ,2 ]
Wang, Xiao-Yuan [1 ,2 ]
Li, Pu [1 ]
Iu, Herbert H. C. [3 ]
Cheng, Zhi-Qun [1 ]
机构
[1] Hangzhou Dianzi Univ, Wenzhou Inst, Wenzhou, Peoples R China
[2] Hangzhou Dianzi Univ, Sch Elect & Informat, Hangzhou, Peoples R China
[3] Univ Western Australia, Sch Elect & Elect Engn, Crawley, WA, Australia
基金
中国国家自然科学基金;
关键词
tri-valued memristor; ternary encoder; ternary decoder; ternary comparator; ternary data selector; CNTFET;
D O I
10.3389/fphy.2023.1292336
中图分类号
O4 [物理学];
学科分类号
0702 ;
摘要
Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring. In contrast to the binary logic circuit design in this method, ternary combinational logic circuit implementation is more complicated. In this paper, a ternary circuit design method that does not require cascading basic ternary logic gates is proposed based on a tri-valued memristor, which can directly realize specific logic functions through a series connection of memristors. The ternary encoder, ternary decoder, ternary comparator, and ternary data selector are implemented by this method, and the effectiveness of the circuits is verified by LTspice simulations.
引用
收藏
页数:12
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