DeBAM - ERCPAA - CNN: Hardware Efficient CNN Accelerator Design Using Decoder Based Low Power Approximate Multiplier and Error Reduced Carry Prediction Approximate Adder

The growth of CNN-based image recognition applications posed the challenge of implementing millions of multiplications and accumulation (MAC) operations on CNNs. Several approximate multipliers are used to decrease the power consumption of CNN. The existing approximate multipliers-based CNN exhibits low efficiency, poor accuracy, high power consumption, and is also time-consuming. This manuscript proposes the Hardware efficiency of CNN Architecture design using Decoder-Based Low Power Approximate Multiplier and Error Reduced Carry Prediction Approximate Adder for Modified National Institute of Standards and Technology (MNIST) dataset Classification. In CNN, MAC is required to execute multiplication. Though, the MAC unit has an issue with area and power consumption. It has a multiplier and accumulator, and multiplier has many logic gates and consumes high power. Decoder-based low power approximate multiplier (DeBAM) and error-reduced carry prediction approximate adder (ERCPAA) are proposed to perform multiplication and addition operations in MAC units of CNN. DeBAM is used for reducing power consumption and design complexity in CNN. Also, ERCPAA is used for lowering path delay and area utilization. The coding is done in Verilog, and the proposed CNN design has been synthesized and implemented on FPGA using Xilinx ISE 14.5 System generator. The performance analysis of the proposed DeBAM-ERCPAA-CNN-based CNN design attains higher speeds of 26.94%, 28.944%, 38.49%, and 33.03% compared with the existing designs. Then the proposed CNN design is imitated with MATLAB/Simulink for MNIST dataset classification. The performance analysis of the proposed DeBAM-ERCPAA-CNN-based plan attains higher accuracy, 32.86%, 31.97%, 14.86%, and 33.86% compared with the existing methods.