Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC

This paper proposes an 8 bit time-interpolated Vernier digital-to-time converter (DTC) consisting of a 4-bit Vernier delay line coarse DTC and a 4 bit time interpolator fine DTC with applications in a time-based successive approximation register time-to-digital converter (SAR TDC) for power and area efficiency. The design, operation, calibration, and error analysis of the DTC are presented. The DTC is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3 device models. Simulation results show that the DTC achieves a resolution of 0.57-0.69 ps, a dynamic range of 145.4-176 ps, and DNL and INL of 0.5 LSB and 0.52 LSB, respectively and consumes 1.1 mW.