Integrated Delay-Line Based High-Resolution PFM-PWM Modulator

This article introduces a new architecture for an all-digital high-resolution variable-frequency variable-duty-cycle modulator. Constructed through digital standard-cell delay-line and simple combinatorial logic, the modulator produces PWM signals with time-resolution of a single delay-element for both switching frequency and duty-cycle attributes, thus making it a promising candidate for integration in hybrid controllers of high frequency resonant converters operating in the MHz range. Since the entire architecture is realized through standard cells, the solution also scales with fabrication technology and is described in HDL, which translates onto hardware using automated process. The modulator has been designed on a 0.18 mu m 5V CMOS platform, totaling 0.18mm(2) of effective silicon area as well as on an Altera FPGA to demonstrate the versatility of the architecture. Experiment results of the FPGA prototype are provided as well as post-layout simulations of the ASIC realization for a variety of mitigation sequences achieving time-resolution of 220ps and 200ps, respectively.