Research on Hardware System of APWL Algorithm Based on FPGA

被引：0
|
作者：
Jiang Leping [1 ]
Bo Xu [2 ]
机构：
[1] Chengdu Univ Technol, Sch Mech & Elect Engn, Chengdu, Peoples R China
[2] Univ Elect Sci & Technol China, Sch Automat Engn, Chengdu, Peoples R China
来源：
2023 3RD ASIA-PACIFIC CONFERENCE ON COMMUNICATIONS TECHNOLOGY AND COMPUTER SCIENCE, ACCTCS | 2023年
关键词：
fractional calculus; fractional order; FPGA; Grunwald-Letnikov; IMPLEMENTATION;
D O I：
10.1109/ACCTCS58815.2023.00133
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper proposes an improved piecewise linear based on the definition of Grunwald-Letnikov, and designs the FPGA implementation scheme of the algorithm. Compared with the previous PWL method, the main advantages of the design in this paper are that the calculation precision of fractional calculus is improved, and the consumption of FPGA hardware resources is greatly reduced. Finally, the algorithm and hardware implementation scheme are verified respectively in Matlab software and digital oscilloscope experiment platform based on FPGA.
引用
收藏
页码：728 / 738
页数：11
相关论文
共 50 条
  • [1] FPGA based hardware implementation of Bat Algorithm
    Ben Ameur, Mohamed Sadok
    Sakly, Anis
    APPLIED SOFT COMPUTING, 2017, 58 : 378 - 387
  • [2] Sports image detection based on FPGA hardware system and particle swarm algorithm
    Hu Jing
    Xing Xiaoqiong
    MICROPROCESSORS AND MICROSYSTEMS, 2021, 80 (80)
  • [3] Hardware/software partitioning and scheduling algorithm based on FPGA
    Li, Lanying
    Chen, Longjuan
    2014 7TH CONFERENCE ON CONTROL AND AUTOMATION (CA), 2014, : 15 - 18
  • [4] Research on the Hardware RBF Fuzzy Neural based on the FPGA
    Xu, Bing
    Guo, Fei
    PROCEEDINGS OF THE 2015 INTERNATIONAL SYMPOSIUM ON COMPUTERS & INFORMATICS, 2015, 13 : 1268 - 1276
  • [5] Hardware implementation of detection algorithm for railway clearance based on FPGA
    Wang, Yao
    Wang, Zhongwei
    Yu, Zujun
    Tiedao Xuebao/Journal of the China Railway Society, 2016, 38 (03): : 84 - 91
  • [6] FPGA based Hardware Accelerator for KAZE Feature Extraction Algorithm
    Kalms, Lester
    Elhossini, Ahmed
    Juurlink, Ben
    2016 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2016, : 281 - 284
  • [7] A Hardware Accelerator for SSD Object Detection Algorithm Based on FPGA
    Xie H.
    Cao J.
    Li P.
    Zhao X.
    Zhang X.
    Beijing Daxue Xuebao (Ziran Kexue Ban)/Acta Scientiarum Naturalium Universitatis Pekinensis, 2022, 58 (06): : 1015 - 1022
  • [8] FPGA-Based Parallel Hardware Architecture For SIFT Algorithm
    Peng, J. Q.
    Liu, Y. H.
    Lyu, C. Y.
    Li, Y. H.
    Zhou, W. G.
    Fan, K.
    2016 IEEE INTERNATIONAL CONFERENCE ON REAL-TIME COMPUTING AND ROBOTICS (IEEE RCAR), 2016, : 277 - 282
  • [9] Design of UCL Hardware Filtering System Based on FPGA
    Ma Jianguo
    Sun Yubo
    Xing Ling
    Ma Qiang
    PROCEEDINGS OF THE 29TH CHINESE CONTROL CONFERENCE, 2010, : 4193 - 4196
  • [10] A hardware implementation in FPGA of the Rijndael algorithm
    Chitu, C
    Chien, D
    Chien, C
    Verbauwhede, I
    Chang, F
    2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS, 2002, : 507 - 510
12345