Hardware Implementation of a Resource-Efficient Router for Multi-Core Spiking Neural Networks

Spiking neural networks (SNNs) are envisioned to be a better alternative to artificial neural networks (ANNs) for targeted applications. Multi-core implementation of SNNs has been built to achieve a resource-efficient design. However, managing the spike traffic congestion while routing the spikes between different cores requires a performance-resource tradeoff to avoid any packet loss. This paper presents a novel router architecture servicing ongoing packets in a 2-D mesh network while guaranteeing no packet drop. Here, the packets are distributed across different paths to reduce spike traffic. The proposed router suitable for a 16x16 network occupies an area of 0.001mm(2) in 28nm CMOS technology, while consuming 75 fJ/transmission.