Adaptive Multioutput Gradient RBF Tracker for Nonlinear and Nonstationary Regression

被引：0

作者：

Sun, Zixuan ^{[1
]}

Wang, Zirui ^{[1
]}

Wang, Runsheng ^{[1
,2
]}

Zhang, Lining ^{[2
,3
]}

Zhang, Jiayang ^{[1
]}

Zhang, Zuodong ^{[1
]}

Song, Jiahao ^{[1
]}

Wang, Da ^{[4
]}

Ji, Zhigang ^{[4
]}

Huang, Ru ^{[1
,2
]}

机构：

[1] Peking Univ, Sch Integrated Circuits, Beijing 100871, Peoples R China

[2] Beijing Adv Innovat Ctr Integrated Circuits, Beijing 100871, Peoples R China

[3] Peking Univ, Sch Elect & Comp Engn, Shenzhen Grad Sch, Shenzhen 518055, Peoples R China

[4] Shanghai Jiao Tong Univ, Natl Key Lab Sci & Technol Micro Nano Fabricat, Shanghai 200240, Peoples R China

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2023年 / 70卷 / 03期

关键词：

Degradation; Aging; Integrated circuit modeling; Stress; FinFETs; Predictive models; Thermal variables control; Circuit reliability; compact aging model; FinFET; mixed-mode degradation; OFF-state degradation; DEGRADATION; MODEL; RELIABILITY; INSTABILITY; NBTI; BTI;

D O I：

10.1109/TED.2023.3239587

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Part I of this article revealed that the OFF-state degradation consists of both bias temperature instability (BTI) and hot carrier degradation (HCD) traps in different channel regions. In part II of this article, a compact aging model of OFF-state degradation in advanced FinFETs is developed and validated by silicon data of 7-nm node, including the degradation and recovery phases. The model is capable to cover various types of devices, such as n/p types, core/IO devices, with short/long-channels. Meanwhile, trap contributions over time in different types of FinFETs are discussed based on the model component analysis. The model is implemented into circuit simulators and used to predict circuit aging with OFF-state degradation, for example, a ring oscillator (RO) circuit. The extrapolation result shows that up to 25% degradation is underestimated if the OFF-state reliability is not considered. This work provides a solution for more accurate reliability evaluation of nanoscale circuit design.

引用

页码：921 / 927

页数：7

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