Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

In this article, Gate-All-Around Lead Zirconate Titanate Negative Capacitance (GAA PZT- NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the RF/Analog applications using Sentauras TCAD simulations. In this study the variation of ferroelectric layer thicknesses (t(fe)) has been systematically investigated. The proposed device yields higher values of on current, transconductance, cut off frequency, TFP, and I-on/I-off ratio and lower values of off current, SS and threshold voltage, compared to baseline device. The proposed device delivers I-on, g(m), f(T), and TFP as 3.38 mA, 9.6 mS, 7.625 THz, and 74.85 THz V-1, respectively which are 220%, 219%, 95% and 259% respectively, higher than the baseline device. Moreover, the I-on/I(off )ratio for the proposed work is 8 x 1013 which is 7.1 x 10(3) times that of baseline device showing a monumental increment in this ratio. Furthermore, the effect of FE thicknesses on various linearity parameters, higher order harmonics, voltage intercept points (VIP2, VIP3), third order power intercept (IIP3) and third order intermodulation distortion (IMD3) have been investigated thoroughly. The proposed device structure offers lower values of higher order harmonics and higher values of voltage intercept points. Also, the IIP3 and IMD3 have been improved. Therefore, the linearity parameters of the device have been significantly improved when compared to the baseline device. The alluring results have been utilized to optimize the bias point of the presented device. Owing to the improved RF/Analog and linearity performance, the presented device could be utilized for imminent next generation low power RFIC applications.