Programming Techniques of Resistive Random-Access Memory Devices for Neuromorphic Computing

Neuromorphic computing offers a promising solution to overcome the von Neumann bottleneck, where the separation between the memory and the processor poses increasing limitations of latency and power consumption. For this purpose, a device with analog switching for weight update is necessary to implement neuromorphic applications. In the diversity of emerging devices postulated as synaptic elements in neural networks, RRAM emerges as a standout candidate for its ability to tune its resistance. The learning accuracy of a neural network is directly related to the linearity and symmetry of the weight update behavior of the synaptic element. However, it is challenging to obtain such a linear and symmetrical behavior with RRAM devices. Thus, extensive research is currently devoted at different levels, from material to device engineering, to improve the linearity and symmetry of the conductance update of RRAM devices. In this work, the experimental results based on different programming pulse conditions of RRAM devices are presented, considering both voltage and current pulses. Their suitability for application as analog RRAM-based synaptic devices for neuromorphic computing is analyzed by computing an asymmetric nonlinearity factor.