C-V measurement and modeling of double-BOX Trap-Rich SOI substrate

被引：3

作者：

Huang, Yang ^{[1
]}

Yan, Yiyi ^{[2
]}

Nabet, Massinissa ^{[2
]}

Liu, Fanyu ^{[1
]}

Li, Bo ^{[1
]}

Li, Binhong ^{[1
]}

Han, Zhengsheng ^{[1
]}

Nguyen, Bich-Yen ^{[3
]}

Cristoloveanu, Sorin ^{[4
]}

Raskin, Jean-Pierre ^{[2
]}

机构：

[1] Chinese Acad Sci, Univ Chinese Acad Sci, Inst Microelect, Key Lab Sci & Technol Silicon Devices, Beijing, Peoples R China

[2] Univ Catholique Louvain UCLouvain, ICTEAM, Leuven, Belgium

[3] SOITEC, Spring Valley, CA USA

[4] INP Grenoble, MINATEC, IMEP, Grenoble, France

来源：

SOLID-STATE ELECTRONICS | 2023年 / 209卷

关键词：

Radio frequency; High resistivity silicon-on-insulator substrate; Polysilicon; Trap density; TCAD simulation; Hysteresis; SI;

D O I：

10.1016/j.sse.2023.108763

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose a new Double-BOX structure for the characterization of the electrical properties of the trap-rich layer used to improve the radio frequency performance of Silicon-on-Insulator substrates. Capacitance voltage (C-V) measurement is used in this investigation. The experiment reveals anomalous C-V behaviors with a plateau appearing in the electron accumulation region and a shift towards negative voltages in hysteresis. According to the TCAD simulation, it is found that both of them are caused by the deep trap states in the polysilicon near the front interface. Based on the C-V hysteresis, the density of the deep trap states can be determined from measurements.

引用

页数：5

共 16 条

[1] C-V characterization of the trap-rich layer in a novel Double-BOX structure
Huang, Yang
Liu, Fanyu
Cristoloveanu, Sorin
Ma, Shiqi
Nabet, Massinissa
Yan, Yiyi
Li, Bo
Li, Binhong
Nguyen, Bich-Yen
Han, Zhengsheng
Raskin, Jean-Pierre
SOLID-STATE ELECTRONICS, 2024, 218
[2] Analysis of anomalous C-V behavior for extracting the traps density in the undoped polysilicon with a double-BOX structure
Huang, Yang
Yan, Yiyi
Nabet, Massinissa
Liu, Fanyu
Li, Bo
Li, Binhong
Han, Zhengsheng
Cristoloveanu, Sorin
Raskin, Jean-Pierre
SOLID-STATE ELECTRONICS, 2024, 217
[3] Effects of Low Boron Concentration on Electrical Properties of Commercial Trap-Rich High Resistivity SOI Substrate
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