Low-stress TSVs for high-density 3D integration

被引：0

作者：

Qiao, Jingping ^{[1
,2
]}

Jiao, Binbin ^{[1
]}

Jia, Shiqi ^{[1
]}

Liu, Ruiwen ^{[1
]}

Yun, Shichang ^{[1
]}

Kong, Yanmei ^{[1
]}

Ye, Yuxin ^{[1
]}

Du, Xiangbin ^{[1
]}

Yu, Lihang ^{[1
,2
]}

Lu, Dichen ^{[1
,2
]}

Liu, Ziyu ^{[1
,2
]}

Wang, Jie ^{[1
,2
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Beijing, Peoples R China

[2] Univ Chinese Acad Sci, Beijing, Peoples R China

来源：

2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC | 2023年

关键词：

Three-dimensional integrated; TSV; Thermal stress;

D O I：

10.1109/ECTC51909.2023.00107

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To address the issue of thermomechanical reliability caused by Through Silicon Via (TSV), this paper proposes a rugby-shaped hollow W-TSV. Simulations and experiments are carried out to study its performance. The simulation results show that the proposed TSV can relieve the thermal stress caused by TSV and has the characteristics of low stress. The maximum thermal stress induced by TSV on the substrate is only 176 MPa, and the thermal stress is reduced by 62.4% and 60.5% along the TSV axial and radial directions, respectively. An ultra-high-density (1600TSVs/mm(2)) TSV array with a size of 640x512, a pitch of 25 mu m, and an aspect ratio of 20.4 was fabricated, and its electrical properties and thermomechanical reliability were tested. The maximum stress on the surface of the TSV array is 31.02 MPa, and the keep-out zone (KOZ) region is not required. The resistance change of TSV after the thermal cycling test is less than 2%. It is demonstrated that the proposed hollow W-TSV has good thermomechanical reliability and electrical properties and can be used for high-density three-dimensional integration.

引用

页码：606 / 611

页数：6

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