Optimization of Slew Mitigation Capacitor in Passive Charge Compensation-Based Delta-Sigma Modulator

被引：2

作者：

Saeed, Mohd Asim ^{[1
,2
]}

Kumar, Manoj ^{[3
]}

Umapathi, B. ^{[3
]}

Das, Devarshi Mrinal ^{[2
]}

机构：

[1] Semicond Lab, VLSI Design Grp, Ajitgarh 160071, India

[2] Indian Inst Technol Ropar, Dept Elect Engn, Rupnagar 140001, India

[3] Semicond Lab, Ajitgarh 160071, India

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2023年 / 70卷 / 06期

关键词：

Slew rate; switched capacitor integrator; passive charge compensation; delta sigma modulator; charge compensation capacitor;

D O I：

10.1109/TCSII.2023.3234909

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief we propose a scheme of optimizing the size of charge compensation (CC) capacitor in a delta-sigma modulator (DSM) using a passive charge compensation (PCC) based switched capacitor integrator (SCI). The slewing behavior of a PCC based SCI is analyzed in both integration phase (IP) and sampling phase (SP) to optimize the size of CC capacitor. The effectiveness of the proposed scheme is demonstrated by implementing a 2-1 cascaded DSM using PCC based SCI with optimized value of CC capacitor in 0.18-mu m CMOS technology. The DSM operates at a frequency of 5-MHz and achieves a peak SNDR of 103.1-dB in the audio bandwidth of 20-kHz. The power consumption of DSM is 220-mu W at a supply voltage of 0.85-V and it consumes 1.3 mm(2) of area. Post-layout simulations show an improvement of 10.8-dB in the SNDR of DSM by using the optimized value of CC capacitor in PCC based SCI.

引用

页码：1821 / 1825

页数：5

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