An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits

In the last decade, resistive random-access memory (RRAM) has been used in designing field-programmable gate arrays (FPGAs). The non-volatility of RRAM has made it a promising substitute for the traditional static random-access memory (SRAM) in emerging non-volatile FPGAs. Most use cases for RRAM in these FPGAs are restricted to the utilization in routing infrastructures and as a one-to-one substitute for the SRAM memory cells in building FPGA lookup tables (LUTs). In contrast, other FPGA building blocks remain the same. These approaches do not fully embrace RRAM as an emerging circuit element beyond memory. In this paper, we introduce an almost fully RRAM-based LUT design. Our design approach relies on RRAM implementing arbitrary Boolean logic in disjunctive normal form. The unique properties of RRAM crossbars are utilized to effectively integrate address decoder and memory in a single crossbar structure, reducing the amount of auxiliary CMOS components. The simulation results show that our RRAM-based LUT design exhibits low energy requirements at sub-picojoule consumption for read operations. Furthermore, it can achieve fast operations at more than 2.5 GHz for read accesses. To show the practicality and usability of our design, we also present an example application.