A 272-341-GHz Integrated Amplifier-Frequency-Doubler Chain in 65-nm CMOS

被引：1

作者：

Yoo, Junghwan ^{[1
]}

Kim, Doyoon ^{[1
]}

Son, Heekang ^{[1
]}

Keum, Wooyong ^{[1
]}

Yang, Sanghyeok ^{[2
]}

Kim, Hyunsoo ^{[2
]}

Rieh, Jae-Sung ^{[1
]}

机构：

[1] Korea Univ, Sch Elect Engn, Seoul 02841, South Korea

[2] Hyundai Motor Co, Fundamental Mat Res Ctr, Uiwang 16082, South Korea

来源：

IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS | 2023年 / 33卷 / 08期

关键词：

CMOS technology; frequency doubler (FD); power amplifier; wideband;

D O I：

10.1109/LMWT.2023.3276170

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents the development of a wideband amplifier-frequency-doubler chain (AFDC) operating at around 300 GHz based on a 65-nm CMOS technology. A new output matching technique for the frequency doubler (FD) is proposed, which provides extensively improved bandwidth and output power compared to a conventional approach often used. In addition, a five-stage transformer-based differential power amplifier has been developed that precedes the FD for sufficient input power and improved overall conversion gain. The integrated AFDC exhibited a measured peak output power of -3.0 dBm along with a 3-dB bandwidth of 69 GHz (272-341 GHz) or a fractional bandwidth of 22%. The measured peak conversion gain is 3.8 dB and the power consumption is 159.6 mW. The chip size is 660 x 155 mu m excluding probing pads.

引用

页码：1215 / 1218

页数：4

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