In-Memory Computing for Machine Learning and Deep Learning

被引:5
|
作者
Lepri, N. [1 ,2 ]
Glukhov, A. [1 ,2 ]
Cattaneo, L. [1 ,2 ]
Farronato, M. [1 ,2 ]
Mannocci, P. [1 ,2 ]
Ielmini, D. [1 ,2 ]
机构
[1] Politecn Milan, Dipartimento Elettron Informaz & Bioingn, I-20133 Milan, Italy
[2] IU NET, I-20133 Milan, Italy
关键词
Random access memory; Nonvolatile memory; Magnetic tunneling; Transistors; FeFETs; Deep learning; Phase change materials; In-memory computing; deep learning; deep neural network; emerging memory technologies matrix-vector multiplication; PHASE-CHANGE MEMORY; CROSSBAR ARRAY; NEURAL-NETWORKS; SRAM MACRO; LINE RESISTANCE; PART I; ACCELERATOR; TECHNOLOGY; DEVICES; STATES;
D O I
10.1109/JEDS.2023.3265875
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In-memory computing (IMC) aims at executing numerical operations via physical processes, such as current summation and charge collection, thus accelerating common computing tasks including the matrix-vector multiplication. While extremely promising for memory-intensive processing such as machine learning and deep learning, the IMC design and realization must face significant challenges due to device and circuit nonidealities. This work provides an overview of the research trends and options for IMC-based implementations of deep learning accelerators with emerging memory technologies. The device technologies, the computing primitives, and the digital/analog/mixed design approaches are presented. Finally, the major device issues and metrics for IMC are discussed and benchmarked.
引用
收藏
页码:587 / 601
页数:15
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