A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC

被引：0

作者：

Lee, Sangyeop ^{[1
]}

Takano, Kyoya ^{[1
]}

Amakawa, Shuhei ^{[1
]}

Yoshida, Takeshi ^{[1
]}

Fujishima, Minoru ^{[1
]}

机构：

[1] Hiroshima Univ, Higashihiroshima 7398530, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2023年 / E106C卷 / 10期

关键词：

sub-sampling PLL; low-supply-voltage; power-scalable; millimeter-wave; CMOS deeply depleted channel (DDC); NOISE;

D O I：

10.1587/transele.2022CTS0001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A power-scalable sub-sampling phase-locked loop (SS-PLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to em-ploying a CMOS deeply depleted channel process (DDC).

引用

页码：533 / 537

页数：5

共 14 条

[1] A 0.4-V 29-GHz-Bandwidth Power-Scalable Distributed Amplifier in 55-nm CMOS DDC Process
Lee, Sangyeop
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Yoshida, Takeshi
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IEICE TRANSACTIONS ON ELECTRONICS, 2022, E105C (10) : 561 - 564
[2] A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS
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[3] A 30 GHz 4.2 mW 105 fsec Jitter Sub-Sampling PLL with 1° Phase Shift Resolution in 65 nm CMOS
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[4] A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS
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[5] A 1.3mW 0.6V WBAN-Compatible Sub-Sampling PSK Receiver in 65nm CMOS
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[7] A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS
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[8] A 30-GHz Digital Sub-Sampling Fractional-N PLL With-238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS
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[9] A 7.9-14.3GHz-243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS
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