CAMP: a hierarchical cache architecture for multi-core mixed criticality processors

被引：0

作者：

Nair, Arun S. ^{[1
]}

Patil, Geeta ^{[2
]}

Agarwal, Archit ^{[1
]}

Pai, Aboli V. ^{[1
]}

Raveendran, Biju K. ^{[1
]}

Punnekkat, Sasikumar ^{[3
]}

机构：

[1] BITS Pilani KK Birla Goa Campus, NH 17B,Bypass Rd, Zuarinagar 403726, Goa, India

[2] BMS Inst Technol & Management, Bengaluru, Karnataka, India

[3] Malardalen Univ, Vasteras, Sweden

来源：

INTERNATIONAL JOURNAL OF PARALLEL EMERGENT AND DISTRIBUTED SYSTEMS | 2024年 / 39卷 / 03期

关键词：

Mixed-criticality systems; cache locking; cache partitioning; hierarchical cache architecture; cache coherence protocol; worst-case execution time (WCET);

D O I：

10.1080/17445760.2023.2293913

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

CAMP proposes a hierarchical cache subsystem for multi-core mixed criticality processors, focusing on ensuring worst-case execution time (WCET) predictability in automotive applications. It incorporates criticality-aware locked L1 and L2 caches, reconfigurable at mode change intervals, along with criticality-aware last level cache partitioning. Evaluation using CACOSIM, Moola Multicore simulator, and CACTI simulation tools confirms the suitability of CAMP for keeping high-criticality jobs within timing budgets. A practical case study involving an automotive wake-up controller using the sniper v7.2 architecture simulator further validates its usability in real-world mixed criticality applications. CAMP presents a promising cache architecture for optimized multi-core mixed criticality systems.<br /> [GRAPHICS]

引用

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页码：317 / 352

页数：36

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