A 13-bit 70MS/s SAR-Assisted 2-bit/cycle Cyclic ADC with Offset Cancellation and Slack-Borrowing Logic

This paper presents an energy and area-efficient successive approximation register (SAR)-assisted cyclic analog-to-digital converter (ADC) architecture. The proposed hybrid ADC combines a 2-bit/cycle cyclic ADC with a slack-borrowing coarse SAR ADC. The proposed multiply-by-one cyclic ADC achieves low-power and 2-bit/cycle operation without any extra hardware cost. The simultaneous amplifier and comparator offset cancellation mitigates the 2nd-stage cyclic ADC offset. Clocked at 70MS/s, the proposed ADC consumes 0.88mW, yielding FoMS and FoMW of 175dB and 6.9fJ/conv, respectively.