Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers

Approximate multipliers are widely used in image processing and multimedia signal processing applications for the reduction in area, computation time, and power consumption. 4:2 compressors play a key role in multipliers for efficient addition of partial product bits. In this paper, an inexact 4:2 compressor is proposed, where a major portion of the logic associated with the generation of Carry and Sum are shared to reduce the logic/circuit complexity. During the design time overestimates are balanced with the underestimates so as to reduce the total error distance. The proposed compressor is used for the addition of partial products of the Baugh-Wooley multiplier. A novel algorithm is proposed for the placement of inexact 4:2 compressors in the partial product bit array, based on the minimum peak signal-to-noise ratio requirement of the application. The approximate multipliers thus obtained are used for edge detection using Sobel operator. It is observed from the Pareto analysis that the proposed design offers significant saving in area, computation time, and power consumption over the design with nearly the same error performance. Besides, the proposed design is more error tolerant compared with the design with nearly the same area-delay trade-off and power-delay trade-off. Moreover, the proposed inexact 4:2 compressor-based Baugh-Wooley multiplier is found to offer better accuracy-area trade-off compared to the state-of-the-art 4:2 compressors in convolutional neural network-based classification.