Graphene-Integrated Negative Quantum Capacitance Field-Effect Transistor With Sub-60-mV/dec Switching

被引：3
|
作者：
Zhu, Hao [1 ]
Yang, Yafen [1 ]
Zhu, Xinyi [1 ]
Raju, Parameswari [2 ,3 ]
Ioannou, Dimitris E. [2 ,3 ]
Li, Qiliang [2 ,3 ]
机构：
[1] Fudan Univ, Sch Microelect, Shanghai 200433, Peoples R China
[2] NIST, Engn Phys Div, Gaithersburg, MD 20878 USA
[3] George Mason Univ, Dept Elect & Comp Engn, Fairfax, VA 22030 USA
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2023年 / 70卷 / 09期
基金：
美国国家科学基金会; 中国国家自然科学基金;
关键词：
2-D metallic system; grapheme; negative quantum capacitance; subthreshold slope (SS); 2-DIMENSIONAL ELECTRON; TOPOLOGICAL-INSULATOR; DIRAC CONE; COMPRESSIBILITY; MOS2;
D O I：
10.1109/TED.2023.3294365
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The aggressive scaling of metal-oxide- semiconductor field-effect transistor (MOSFET) has urged advanced device technology overcoming the 60-mV/dec limit of subthreshold slope (SS) at room temperature. The introduction of a negative component in the FET gate capacitance has been proven effective to realize steep-slope switching. Here, we report a sub-60-mV/dec MoS2 negative quantum capacitance FET (NQCFET) with single-layer (SL) graphene integrated in the gate-stack. The negative quantum capacitance from the low density of states (DOS) is strongly associated with the electron system of the 2-D SL graphene. With this negative contribution to the gate capacitance, subthermionic switching is achieved in the NQCFET with a minimum SS of 31 mV/dec. This prototype device illustrates a feasible approach to realize negative quantum capacitance in an FET architecture and opens attractive pathways for future steep-slope and low-power electronic device applications.
引用
收藏
页码：4899 / 4904
页数：6
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