共 50 条
- [43] Implementation of Turbo decoder implemented on a 32-bit fixed-point DSP Beijing Youdian Xueyuan Xuebao/Journal of Beijing University of Posts And Telecommunications, 2001, 24 (01): : 12 - 16
- [45] Design of 16-bit fixed-point CNN coprocessor based on FPGA 2018 IEEE 23RD INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP), 2018,
- [46] Bit-Precise Verification of Discontinuity Errors Under Fixed-Point Arithmetic SOFTWARE ENGINEERING AND FORMAL METHODS (SEFM 2021), 2021, 13085 : 443 - 460
- [47] Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs Journal of Signal Processing Systems, 2017, 89 : 293 - 317
- [48] Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2017, 89 (02): : 293 - 317
- [49] Laius: An 8-bit Fixed-point CNN Hardware Inference Engine 2017 15TH IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS AND 2017 16TH IEEE INTERNATIONAL CONFERENCE ON UBIQUITOUS COMPUTING AND COMMUNICATIONS (ISPA/IUCC 2017), 2017, : 143 - 150
- [50] Implementation of turbo decoder implemented on a 32-bit fixed-point DSP Beijing Youdian Daxue Xuebao/Journal of Beijing University of Posts and Telecommunications, 2001, 24 (01): : 12 - 16