Design of high-efficiency complex multiplier for fault-tolerant computation

In this paper, two improved structures and a truncation strategy with compensation for complex multiplication are proposed. Simulation in 28-nm CMOS for hardware performance is provided. Compared to the general complex multiplier, the two accurately improved structures realize 18.58% and 20.80% power consumption reduction, respectively. The truncation strategy with compensation reduces power consumption by 46.8% and controls Mean Relative Error Distance (MRED) at 0.54%. To verify the practicability of the proposed architec-ture, our designs are applied to the Fast Fourier Transform (FFT) processor to comprehensively evaluate the error characteristics and circuit performance.