Random Flip Bit Aware Reading for Improving High-Density 3-D NAND Flash Performance

被引:3
|
作者
Feng, Hua [1 ]
Wei, Debao [1 ]
Gu, Shipeng [2 ]
Piao, Zhelong [1 ]
Wang, Yongchao [1 ]
Qiao, Liyan [1 ]
机构
[1] Harbin Inst Technol, Sch Elect & Informat Engn, Harbin 150080, Peoples R China
[2] Chinese Flight Test Estab, Xian 710089, Peoples R China
关键词
Flash memories; Calibration; Threshold voltage; Reliability; Parity check codes; Optimization; Decoding; 3-D NAND flash; read reference voltage; storage reliability; random read error; memory test; STRATEGY; VOLTAGE;
D O I
10.1109/TCSI.2024.3366902
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
With the explosive growth of data storage demands, the storage density of flash memory continues to increase. However, the reliability and read performance of high-density flash memory are constantly declining. To address this issue, this study proposes a low-cost read reference voltage (RRV) calibration strategy based on random bit flips. In this study, the relationship between the random bit flips count (RFBC) of flash memory and the read reference voltage offset level (RRVOL) is characterized, and an RFBC-RRVOL conversion model is constructed. Subsequently, the characteristics of 3D flash memory RRV offset are thoroughly studied, and based on the observation results. A RRV grouping optimization scheme and RRV calibration range WL expansion scheme are proposed to achieve generalized calibration of all WLs in flash memory blocks. Experimental results indicate that the proposed strategy introduces a minimal storage overhead of only 15.26 KB, which reduces the raw bit error rate (RBER) of flash memory at the end of life (EOL) and increases the success rate of one time read to 99.89%. Such improvements greatly enhance the reliability of data storage and reading performance. These results demonstrate that the strategy has good practicality and effectiveness in addressing the reliability and read performance issues of high-density flash memory.
引用
收藏
页码:2372 / 2383
页数:12
相关论文
共 50 条
  • [1] Optimizing Lifetime Capacity and Read Performance of Bit-Alterable 3-D NAND Flash
    Chen, Shuo-Han
    Yang, Ming-Chang
    Chang, Yuan-Hao
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2021, 40 (02) : 218 - 231
  • [2] Read latency variation aware performance optimization on high-density NAND flash based storage systems
    Shi, Liang
    Lv, Yina
    Luo, Longfei
    Li, Changlong
    Xue, Chun Jason
    Sha, Edwin H-M
    CCF TRANSACTIONS ON HIGH PERFORMANCE COMPUTING, 2022, 4 (03) : 265 - 280
  • [3] Read latency variation aware performance optimization on high-density NAND flash based storage systems
    Liang Shi
    Yina Lv
    Longfei Luo
    Changlong Li
    Chun Jason Xue
    Edwin H.-M. Sha
    CCF Transactions on High Performance Computing, 2022, 4 : 265 - 280
  • [4] Scrubbing-Aware Secure Deletion for 3-D NAND Flash
    Wang, Wei-Chen
    Ho, Chien-Chung
    Chang, Yuan-Hao
    Kuo, Tei-Wei
    Lin, Ping-Hsien
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (11) : 2790 - 2801
  • [5] High-Density 3-D NAND Cell Array Design With Hybrid Bonding
    Lee, Seungmin
    Lim, Joonsung
    Kim, Jun Hyoung
    Cho, Sunghwan
    Lee, Yong Kyu
    Choi, Byoungdeog
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 70 (11) : 5638 - 5644
  • [6] Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash
    Wu, Fei
    Zhang, Meng
    Du, Yajuan
    Liu, Weihua
    Lu, Zuo
    Wan, Jiguang
    Tan, Zhihu
    Xie, Changsheng
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (04) : 909 - 921
  • [7] Improving Read Performance Via Selective Vpass Reduction on High Density 3D NAND Flash Memory
    Li, Qiao
    Shi, Liang
    Di, Yejia
    Du, Yajuan
    Xue, Chun Jason
    Yang, Chengmo
    Zhuge, Qingfeng
    Sha, Edwin H. M.
    2017 IEEE 6TH NON-VOLATILE MEMORY SYSTEMS AND APPLICATIONS SYMPOSIUM (NVMSA 2017), 2017,
  • [8] Impact of Cycling on Random Telegraph Noise in 3-D NAND Flash Arrays
    Nicosia, Gianluca
    Goda, Akira
    Spinelli, Alessandro S.
    Compagnoni, Christian Monzio
    IEEE ELECTRON DEVICE LETTERS, 2018, 39 (08) : 1175 - 1178
  • [9] Vertical Structure NAND Flash array integration with paired FinFET multi-bit scheme for high-density NAND Flash memory application
    Koo, June-Mo
    Yoon, Tae-Eung
    Lee, Taehee
    Byun, Sungjae
    Jin, Young-Gu
    Kim, Wonjoo
    Kim, Sukpil
    Park, Jongbong
    Cho, Junseok
    Choe, Jeong-Dong
    Lee, Choong-Ho
    Lee, Jong Jin
    Han, Je-Woo
    Kang, Yunseung
    Park, Sangjun
    Kwon, Byoungho
    Jung, Yong-Ju
    Yoo, Inkyoung
    Park, Yoondong
    2008 SYMPOSIUM ON VLSI TECHNOLOGY, 2008, : 93 - +
  • [10] Towards Improving Ionizing Radiation Tolerance of 3-D NAND Flash Memory
    Ray, Biswajit
    Buddhanoy, Matchima
    Kumar, Mondol Anik
    2023 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW, 2023, : 109 - 112