DTMOS Based Low Power Adaptively Biased Fully Differential Transconductance Amplifier with Enhanced Slew-Rate and its Filter Application

An efficient implementation of low-voltage low power two stage fully differential transconductance amplifier using CMOS technology is proposed. In this work, the dynamic threshold voltage MOSFET (DTMOS) and unique adaptive biasing technique are used to obtain the enhanced slew-rate with minimized power supply overhead. This dynamic threshold MOS based fully differential OTA operates at +/- 0.5 V dual supply voltage. It provides average slew-rate as168 V/mu S with 0.104 mW static power consumption. The dc gain of the circuit is calculated as 73.86 dB with a 72 degrees phase margin. The figure of merit of proposed OTA is 16.15 [(V/mu s).pF/mu W] for the load capacitor of 10 pF, which shows significant improvement compared to prior work. To validate the robustness of the proposed design universal voltage mode filter is designed and simulated as its application. Mentor Graphics Eldospice with 0.18 mu m TSMC level 53 CMOS technology has been used to verify the performance of the proposed circuit and its application.