MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles

General Sparse Matrix-Matrix Multiplication (SpGEMM) which involves product of two sparse matrices is a key operation in many deep learning algorithms. Sparse matrices consist of only a few non-zero elements which makes it inefficient to use conventional matrix multiplication algorithms. Hence, specialized architectures for sparse matrix multiplication have been proposed. Prior works in this field uses outer product based implementation and they suffer due to poor load balance in the processing elements. We propose a modified outer product based sparse matrix-matrix multiplication architecture with configurable tiles, referred as MOSCON, which can be accelerated on Field Programmable Gate Arrays (FPGA). MOSCON can perform sparse matrix multiplication of any dimensions and takes the advantages of outer product implementation along with the features of load balanced architecture. Proposed architecture has been implemented on Xilinx Kintex-7 FPGA device and gives an average performance gain of 9.21% when compared with state-of-the-art implementations.