Design and readout architecture of a monolithic binary active pixel sensor in TPSCo 65 nm CMOS imaging technology

被引:5
|
作者
Cecconi, L. [1 ]
Piro, F. [1 ,7 ]
Melo, J. L. A. de [1 ]
Deng, W. [1 ,2 ]
Hong, G. H. [1 ,5 ]
Snoeys, W. [1 ]
Mager, M. [1 ]
Suljic, M. [1 ]
Kugathasan, T. [1 ]
Buckland, M. [8 ]
Rinella, G. Aglieri [1 ]
Leitao, P. V. [1 ]
Reidt, F. [1 ]
Baudot, J. [1 ]
Bugiel, S. [4 ]
Colledani, C. [4 ]
Contin, G. [8 ]
Hu, C. [4 ]
Kluge, A. [1 ]
Kluit, R. [3 ]
Vitkovskiy, A. [3 ]
Russo, R. [3 ]
Becht, P. [1 ]
Grelli, A. [3 ]
Hasenbichler, J. [1 ]
Munker, M. [1 ]
Soltveit, H. K. [6 ]
Menzel, M. W. [6 ]
Sonneveld, J. [3 ]
Tiltmann, N. [9 ]
机构
[1] CERN, Geneva, Switzerland
[2] Cent China Normal Univ, Wuhan, Peoples R China
[3] NIKHEF, Amsterdam, Netherlands
[4] IPHC, Strasbourg, France
[5] Yonsei Univ, Seoul, South Korea
[6] Heidelberg Univ, Heidelberg, Germany
[7] Ecole Polytech Fed Lausanne, Lausanne, Switzerland
[8] Univ & INFN Trieste, Trieste, Italy
[9] Univ Munster, Munster, Germany
来源
JOURNAL OF INSTRUMENTATION | 2023年 / 18卷 / 02期
关键词
Electronic detector readout concepts (solid-state); Particle tracking detectors (Solid-state detectors); Solid state detectors;
D O I
10.1088/1748-0221/18/02/C02025
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65 nm ISC process in the framework of the CERN-EP R & D on monolithic sensors and the ALICE ITS3 upgrade. It features a 32 x 32 binary pixel matrix at 15 mu m pitch with event-driven readout, with GHz range time-encoded digital signals including Time-Over-Threshold. The chip proved fully functional and efficient in testbeam allowing early verification of the complete sensor to readout chain. This paper focuses on the design, in particular the digital readout and its perspectives with some supporting results.
引用
收藏
页数:10
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