An 8T SRAM Based Digital Compute-In-Memory Macro For Multiply-And-Accumulate Accelerating

Compute-in-memory (CIM) has been a promising technology to reduce the data movement energy and latency, which is the bottleneck of Von Neumann architecture. Digital approaches in CIM macro have many advantages compared with analog counterparts, such as programmability and inference precision. However, previous works with digital approaches generally employ complex SRAM bit-cells and computational components, which cause a large area overhead. In this paper, we propose a new 8T SRAM bit-cell to reduce the overall area of the SRAM array, which is able to implement the 1-bit multiplication without read-disturb issue. Additionally, the interleaving adder tree and dual supply voltage strategy are employed for further reduction on area and power consumption of computational circuits. Besides, a result combination circuit is designed to increase the bit-precision flexibility. A 16Kb SRAM CIM macro with proposed techniques is designed in a 40-nm CMOS technology. The simulation results show that our work achieves 820 GOPS throughput and 94 TOPS/W energy efficiency with 4-b of both input and weight. It achieves 1.3x higher energy efficiency and 70% area reduction when compared to the recent state-of-the-art works.