Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors

被引：0
|
作者：
Shin, Hye-Ju [1 ]
Jo, Sung-Hun [1 ]
机构：
[1] Department of Nano & Semiconductor Engineering, Tech University of Korea, Siheung,15073, Korea, Republic of
来源：
Applied Sciences (Switzerland) | 2024年 / 14卷 / 23期
关键词：
Cellular arrays - Dynamic random access storage - Low power electronics - Memory architecture - Programmable logic controllers - Static random access storage - System-on-chip;
D O I：
10.3390/app142310924
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [1] An 8T SRAM Based Digital Compute-In-Memory Macro For Multiply-And-Accumulate Accelerating
    Wang, Zilin
    Luo, Hongyang
    Peng, ZeYang
    Chao, Xingchen
    He, Yajuan
    [J]. 2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS, 2023,
  • [2] Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks
    Yu, Chengshuo
    Yoo, Taegeun
    Kim, Tony Tae-Hyoung
    Kim, Bongjin
    Chuan, Kevin Chai Tshun
    [J]. 2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020), 2020, : 175 - 176
  • [3] A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips
    Zhang, Chuanghao
    Wang, Mingyu
    Mai, Yangzhan
    Tang, Chengcheng
    Yu, Zhiyi
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (09) : 3589 - 3593
  • [4] A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks
    Yu, Chengshuo
    Yoo, Taegeun
    Chai, Kevin Tshun Chuan
    Kim, Tony Tae-Hyoung
    Kim, Bongjin
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (11) : 3466 - 3476
  • [5] A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks
    Kim, Youngbae
    Li, Shuai
    Yadav, Nandakishor
    Choi, Kyuwon Ken
    [J]. ELECTRONICS, 2021, 10 (17)
  • [6] 8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator
    Jiang, Hongwu
    Liu, Rui
    Yu, Shimeng
    [J]. 2020 IEEE 63RD INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2020, : 257 - 260
  • [7] 8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips
    Su, Jian-Wei
    Lu, Pei-Jung
    Wu, Ping-Chun
    Chou, Yen-Chi
    Liu, Ta-Wei
    Chung, Yen-Lin
    Hung, Li-Yang
    Ren, Jin-Sheng
    Huang, Wei-Hsing
    Chien, Chih-Han
    Mei, Peng-, I
    Li, Sih-Han
    Sheu, Shyh-Shyuan
    Lo, Wei-Chung
    Chang, Shih-Chieh
    Hong, Hao-Chiao
    Lo, Chung-Chuan
    Liu, Ren-Shuo
    Hsieh, Chih-Cheng
    Tang, Kea-Tiong
    Chang, Meng-Fan
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71 (04) : 2304 - 2308
  • [8] Analog Compute-in-Memory For AI Edge Inference
    Fick, D.
    [J]. 2022 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM, 2022,
  • [9] Resonant Compute-In-Memory (rCIM) 10T SRAM Macro for Boolean Logic
    Challagundla, Dhandeep
    Bezzam, Ignatius
    Saha, Biprangshu
    Islam, Riadul
    [J]. 2023 IEEE 41ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD, 2023, : 110 - 117
  • [10] A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices
    Chiu, Yen-Cheng
    Khwa, Win-San
    Yang, Chia-Sheng
    Teng, Shih-Hsin
    Huang, Hsiao-Yu
    Chang, Fu-Chun
    Wu, Yuan
    Chien, Yu-An
    Hsieh, Fang-Ling
    Li, Chung-Yuan
    Lin, Guan-Yi
    Chen, Po-Jung
    Pan, Tsen-Hsiang
    Lo, Chung-Chuan
    Liu, Ren-Shuo
    Hsieh, Chih-Cheng
    Tang, Kea-Tiong
    Ho, Mon-Shu
    Lo, Chieh-Pu
    Chih, Yu-Der
    Chang, Tsung-Yung Jonathan
    Chang, Meng-Fan
    [J]. NATURE ELECTRONICS, 2023, 6 (07) : 534 - +
12345