Detecting Hardware Faults in Approximate Adders via Minimum Redundancy

Approximate Computing (AC) is an emerging design paradigm that exploits the error-resiliency of specific applications to trade-off between accuracy, performance, area, and power. Nonetheless, fault tolerance remains an open issue in AC since hardware (HW) faults that are caused, for example, by radiation-induced effects, environmental disturbances, or aging/wear-out phenomena, can lead to an arithmetic error out of application specification boundaries. In this work, we guard approximate adders against HW faults by selectively inserting Hardware Fault Detection (HFD) redundancy, i.e., parity code/parity prediction or Double Modular Redundancy (DMR) into the Approximate Arithmetic Circuits (AACs). Specifically, we insert HFD only to the 1-bit adder cells of AACs that can cause an arithmetic error out of their specifications when corrupted by HW faults. Therefore, our proposed approach introduces less area and delay overheads than blindly duplicating the whole AAC. We employ our methodology to state-of-the-art approximate adder models (either low-latency approximate adder or approximate full adder models) to prove that our proposed technique inserts HFD into the AACs without negating their original approximation gains.